Tuesday, February 8, 2011

Current Vacancy of Lead Member Technical Staff \ 50314666 in Mentor Graphics india

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Job ID: 50314666E
Location: Noida, India

Be an integral part of a team to validate verification ip, such as PCI Express and 10 Gigabit Ethernet, for use with Questa RTL simulation. These verification ip help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test, validate and manage regression tests for standard verification ip for a wide range of end user applications, as well as custom protocols ips for specific customers. You will interact with TMEs and CSDs or directly with customers to resolve customer issues.


Solid Verilog HDL RTL knowledge • Solid RTL simulation and test bench experience • Intimate knowledge of one or more standard bus protocols • Solid engineering • MS/BE and 2-5 years in electrical engineering or related field.

For Further information and apply online : http://www.mentor.com

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